1. Field
The present disclosure relates generally to a semiconductor memory device, and, more particularly, to a non-volatile memory device and a method thereof capable of verifying programming of a desired group of cells. The non-volatile memory device includes a current sensing checking block for verifying programming of a desired group of cells of a memory array. The current sensing checking block may be a compensated current sensing checking block.
The disclosure also relates to a memory device and method for compensating mismatch of resistances and internal offset of an operational amplifier.
2. Description of the Related Art
Among the various types of flash memory devices, NAND-type flash memory devices are increasingly used as high capacity data storage media. Each cell of a flash memory is programmed to store information by trapping electrons in a floating gate. The programming operation is performed by driving a high current through the drain and source of the cell while driving a programming voltage to the control gate of the cell, an operation known as hot electron injection. The control gate is connected to a word-line of the flash memory, and voltage is provided to the control gate through the word-line.
Each memory cell can store a single bit which is referred to as a single level memory cell (SLC), or alternatively, each cell can store multiple bits which is referred to as a multiple level memory cell (MLC). In both of the SLC and the MLC, the information stored in each cell is defined by a corresponding threshold voltage of the memory cell.
There is also the NOR-type flash memory. The main difference between NAND-type and NOR-type flash memories is that the NAND-type memory requires cells in the same string being serially connected with each other by drain and source while each cell of a NOR-type flash memory is directly connected to the bit-line and to the source line.
FIG. 1 schematically shows an exemplary arrangement of cells, string, word-lines and bit-lines of a NAND type flash memory.
In FIG. 1, there are shown four strings 110 in total in a main memory array of the NAND type flash memory. Each string 110 includes four cells 130. Each cell can store one-bit or several bits of information in its floating gate as explained above for the SLC or the MLC. In each string, the drain of one cell is connected to the source of another cell. The drain selection transistor DST and the source selection transistor SST can be used to address the cells. Each bit-line BL0 or BL1 is connected to the DST of each string.
The word-lines WL0 to WL7 indicate the selected page for the programming, which the voltage pulse is applied to, having amplitude characteristics and duration of a typical programming phase. The bit-line BL0 or BL1 is in particular the electrical connection between the cell and the reference page buffer (not illustrated).
Programming operation can be performed in different modes. One mode to program a desired cell is using the incremental step pulse program (ISPP). The ISPP scheme drives an incremental pulse with a specific period on the control gate of the desired cell through the corresponding word-line. The ISPP scheme can improve the correction and speed of the programming operation. Another programming algorithm other than the ISPP can also be used.
After each programming operation is terminated or each pulse of the ISPP is driven to the cell, it can be verified whether programming for a certain address page is successful or not. Based on the result of the verification, a controller can determine whether to proceed with the programming of other memory cells (i.e., other addresses) or to continue to program the same cells by applying a pulse with different electrical characteristics (e.g., greater width).
The verify operation is performed by pre-charging the bit-line BL0 or BL1 to a known voltage value VPRE and applying a voltage of “verification” to the word-line. For example, when the cells of the word-line WL1 are to be verified, the voltage value VPRE is driven to WL1. Non-addressed word-lines WL0, WL2 and WL3 are driven a pass-voltage during reading.
When the memory cell is programmed and then its relative electrical threshold has been changed to a higher value, the corresponding bit-line will not discharge and will be maintained at the voltage value VPRE, since the “verification” voltage is lower than the threshold voltage and thus not able of switching on the corresponding cell. The charged amount may diminish by a small amount due to intrinsic leakage.
When the memory cell is not programmed, the corresponding bit line will tend to discharge to a value tending to zero since the threshold voltage of the corresponding cell is low and by driving the “verification” voltage to the corresponding cell switches on. The other cells in the same string are switched on by the pass voltage provided to their control gate. The voltage of the bit-line is discharged to the source line SL connected to the source of the source selection transistor SST.
FIG. 2 schematically illustrates a latch 200 in the page buffer storing the programming status information of the corresponding cell. The discharge of the bit lines BL0 and BL1 is detected by the latch 200, inside the page buffer, which switches and imposes two stable states at the two sides of the latch 200. The latch 200 may include two inverters in feedback to one another and the two nodes in common are identified with QS and QS_N.
When the cell is programmed after the verification operation, the corresponding bit-line does not discharge as explained above. So, the node QS_N is set as the supply voltage VDD or higher. The node QS is set as the ground voltage. When the cell is not programmed after the verification operation, the corresponding bit-line discharges as explained above. So, the QS_N is set as the ground voltage. The QS is set as the supply voltage VDD.
The programming verification also includes counting the number of programming failures so as to determine whether the number of programming failures is tolerable or not by comparing it with a reference number of allowable failures. In particular, the reference number of allowable failures may correspond to the maximum number of errors that can be corrected by an error correction system included the memory.
For performing a programming verification operation, we have found out that it is preferable to implement a dedicated logic block, hereinafter referred to as a current sensing checking block. Due to the difference of physical layouts between the page buffer realized within the memory area and the dedicated logics realized within the peripheral area, the aforementioned comparison may not be performed adequately correctly and compensation of the current sensing checking block may be needed.